A general CMOS semiconductor integrated circuit (hereinafter referred to as "CMOSLSI") is shown in FIG. 1, and FIG. 2 is a conventional BiCMOS semiconductor integrated circuit (hereinafter referred to as "BiCMOSLSI").
For the conventional BiCMOSLSI, in CMOSLSI, a CMOS logical gate circuit 25 in a position where a high load capacity is driven is replaced with a BiCMOS logical gate circuit 26 to enhance the load driving ability of a gate for driving a high load capacity, offering acceleration.
In the design of semiconductor integrated circuits, in order to simplify the design, it is common practice to use a method wherein a logical macro library containing a large variety of logical macros for realizing various logical functions is provided and the logical macros are connected by automatic programmed disposition/wiring or by manual disposition/wiring to realize a desired logical function.
FIG. 3 shows one example of a circuit wherein an inverter is constructed by a BiCMOS logical gate circuit (Japanese Patent Application No. 78297/1994).
The circuit comprises: a first NPN bipolar transistor (hereinafter referred to as "NPN transistor") 27 comprising a collector connected to a high-potential power source (hereinafter referred to as "VCC") 1 and an emitter connected to an output terminal 4; a second NPN transistor 28 comprising a collector connected to an output terminal 4 and an emitter connected to a low-potential power source (hereinafter referred to as "GND"); a P channel MOS transistor (hereinafter referred to as "PMOS") 29 comprising a source connected to VCC1, a drain connected to the base of the first NPN transistor 27, and a gate connected to an input terminal 3; a first N channel MOS transistor (hereinafter referred to as "NMOS") 30 comprising a source connected to GND2 and a drain connected to the base of the first NPN transistor 27; a second NMOS 31 comprising a source connected to the base of the second NPN transistor 28, a drain connected to an output terminal 4, and a gate connected to an input terminal 3; and a resistance element 32 connected between the base of the second NPN transistor 28 and GND 2.
The operation of the conventional BiCMOS logical gate circuit will be briefly described.
At the outset, the operation of the circuit in the case of transition of the input logical level from a high potential to a low potential will be described. When PMOS 29 is turned on and the first NMOS 30 is turned off, the base potential of the first NPN transistor 27 is increased and the first NPN transistor 27 is turned on, pulling up the potential of the output terminal 4. At the same time, NMOS 31 is turned off and the base potential of the second NPN transistor 28 is decreased by the resistor 32 to GND, causing the second NPN transistor 28 to be turned off. This prevents passing of current across the first NPN transistor 27 and the second NPN transistor 28. The above operation results in the transition of the output logical level from a low potential to a high potential.
Next, the operation of the circuit in the case of transition of the input logical level from a low potential to a high potential will be described.
PMOS 29 is turned off, and the first NMOS 30 is turned on. This causes the base potential of the first NPN transistor 27 to be decreased, and the first NPN transistor 27 is turned off. At the same time, the second NMOS 31 is turned on, and the second NPN transistor 28 is turned on, resulting in the transition of the output logical level from a high potential to a low potential.
One example of the circuit constant of the BiCMOS logical gate circuit will be described.
For the NPN transistors 27, 28, the emitter size is 1.2.times.12 .mu.m, PMOS 29 has a gate length of 1.4 .mu.m and a gate width of 20 .mu.m, NMOS 30 has a gate length of 1.2 .mu.m and a gate width of 5 .mu.m, and NMOS 31 has a gate length of 1.2 .mu.m and a gate width of 10 .mu.m.
The voltage VGS applied to the second NMOS 31 is expressed by the following formula: EQU VGS=VIN-VBE
wherein VIN represents the input voltage and VBE represents the voltage across the base and the emitter of the second NPN transistor 28.
If the BiCMOS logical gate circuit in question is driven by the BiCMOS logical gate circuit, the input voltage VIN is expressed by the following formula: EQU VIN=VCC-VBE
wherein VIN represents the input voltage and VCC represents the power source voltage. Therefore, VGS=VCC-2VBE.
Lowering the power source voltage VCC is a technical trend in recent years. In this case, however, as can be seen from the above formula, the VGS applied to the second NMOS 31 is rapidly lowered. In order to satisfactorily shorten the time taken for charging of the base of the second NPN transistor 28, it is necessary to maintain the drain current of the second NMOS 31 on a satisfactorily high level. Lowering the power source voltage VCC for this purpose necessitates satisfactorily increasing the gate width of the second NMOS 31.
This, therefore, renders the input capacity of the BiCMOS logical gate circuit very large. When the BiCMOS logical gate circuit is driven by the CMOS logical gate circuit, the input high level is equal to VCC. This reduces the above influence. Even in this case, the influence is not completely eliminated.
When the input capacity of the BiCMOS logical gate circuit is determined in the large load drive position, the input capacity of the CMOS logical gate circuit is usually made equal to the input capacity of the BiCMOS logical gate circuit. The reason for this is as follows. When the input capacity of the CMOS logical gate circuit is smaller than the input capacity of the BiCMOS logical gate circuit, the delay time in the case of driving of BiCMOS logical gate circuit from CMOS logical gate circuit becomes large. On the other hand, even when the input capacity of the CMOS logical gate circuit is made larger than the input capacity of the BiCMOS logical gate circuit, the delay time cannot be sufficiently shortened, posing significant problems such as increased power consumption and lowered integration density.
It is well known that the power consumption is governed by power for charge and discharge of parasitic capacity of the MOS transistor and, hence, proportional to the gate width. Further, when the wiring between the logical gates is satisfactorily short, the delay time of the CMOS logical gate circuit does not depend upon the gate width of the MOS transistor used. The reason for this is that the travel time for carrier immediately under the gate does not depend upon the gate width and, further, the charge/discharge time for parasitic capacity too does not depend upon the gate width. That the charge/discharge time for parasitic capacity too does not depend upon the gate width can be easily understood from the fact that all the drain current, gate capacity, and source and drain diffusing capacity are proportional to the gate width.
In the conventional BiCMOSLSI, when a BiCMOS buffer section is used for driving large load, such as inter-macro capacity, the gate width of the CMOS logical gate circuit for driving it should be increased because the input capacitance of the BiCMOS buffer is large. In particular, when the power source voltage is low, this tendency is significant.
Therefore, there is a drawback that wasteful power consumption for charge and discharge of gate capacity, diffusion capacity or the like occurs within macros where wiring capacity or the like can be negligible. Further, the size of the MOS transistor is large, and the integration of the bipolar transistor together with the MOS transistor has rendered the integration density smaller than that of CMOSLSI.